英特尔揭开全球首款14纳米处理器Broadwell面纱

上网时间: 2014年08月12日? 我来评论 【字号: ? ?小】

关键字:英特尔14纳米? Broadwell? 14纳米处理器?

Intel Outlines 14nm, Broadwell

Rick Merritt

SANTA CLARA, Calif. -- Intel provided the first details of its 14nm process technology, now qualified for volume production in an Oregon fab, and gave a sneak peak at Broadwell, its first CPU to use it.

Intel claims its 14nm process delivers a lower cost per transistor than its 22nm node thanks to aggressive area scaling using self-aligned double-patterning lithography. It said the process will enable a new class of x86-based 2-in-1 tablet/notebooks less than 9 mm thick that will be on store shelves before the end of the year.

Intel reserved details of Broadwell products until its annual developer forum in San Francisco next month. But it did give some specs for its 14nm FinFETs. Compared to Intel's 22nm process, it will have:

42nm fin pitch, down .70x

70nm gate pitch, down .78x

52nm interconnect pitch down .65x

42nm high fins, up from 34nm

a 0.0588 micron2 SRAM cell, down .54x

~0.53 area scaling compared to 22nm

Products using the 14nm process have been delayed nearly a year due to yield problems. "Scaling the gate and fin pitches as aggressively as we have were reasons for yield challenges, but we are in a very healthy range now and will continue to improve," said Mark Bohr, a senior fellow for the company's logic development group.

Mark Bohr holds a 14nm Intel wafer.

Mark Bohr holds a 14nm Intel wafer.

The area shrinks came in part from building taller fins packed more closely together. The shrinks were needed to overcome wafer costs, which rose faster than normal with a new node due to the need for double patterned lithography. Intel rejected the litho etch/litho etch technique, using instead self-aligned double-patterning.

Netting out rising wafer costs and shrinking transistors "for Intel, cost per transistor continues to come down, if anything at a slightly faster rate," said Bohr.

He claimed Intel still has a significant lead over the rest of the chip industry despite delays of nearly a year in shipping 14nm products. "Intel is shipping a second generation of FinFET technology before others shipped their first," he said. With previous planar nodes, "others have tended to have better density than Intel but came to market later," he noted.

Bohr's comparison of Intel versus industry process technology progress.

Bohr's comparison of Intel versus industry process technology progress.

Intel would not comment on when it will have a 14nm smartphone SoC or the impact it hopes Broadwell will have on sales of x86 tablets or notebooks.

Next page: Comparing fins

Comparing fins

Intel built taller fins packed more closely together to reduce chip area more than normal, compensating for the cost of double patterning.

Intel built taller fins packed more closely together to reduce chip area more than normal, compensating for the cost of double patterning.

Next page: Comparing packages

Comparing packages

Broadwell is 50% smaller in x/y size and 30% smaller in height, in part to accommodate tablets. The package shrink comes in part from more integrated passives (below).

Broadwell is 50% smaller in x/y size and 30% smaller in height, in part to accommodate tablets. The package shrink comes in part from more integrated passives (below).

Next page: Comparing SRAMs

Comparing SRAMs

Intel crafted a tighter SRAM cell for Broadwell.

Intel crafted a tighter SRAM cell for Broadwell.

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