PCIe进军移动领域,踩Thunderbolt地盘

上网时间: 2013年07月02日? 作者:Rick Merritt? 我来评论 【字号: ? ?小】

关键字:PCIe? 移动版PCIe? PCI Express?

Slideshow: PCIe takes on mobile, Thunderbolt, more

Rick Merritt

PCI Express Gen 3 will ride the MIPI M-PHY in tablets and smartphones thanks to one of several new specs from the PCI SIG. SANTA CLARA, Calif. – The spec is done for a mobile interconnect that will pack PCI Express into smartphones and tablets. Cadence and Synopsys showed working silicon for the M-PCIe interface at the annual meeting of the PCI Special Interest Group here.

The spec lets PCIe protocols ride the M-PHY defined by the MIPI trade group and already widely used in mobile devices. OEMs will adopt the interface to lower costs and shrink development times by reusing PCIe software to replace a wide variety of mobile interconnect protocols.

Separately, the PCI SIG expects to finish work before June 2014 on OcuLink, a 32 Gbit/second cabled version of PCIe. It aims to deliver more bandwidth than the rival Thunderbolt interconnect backed by Apple and Intel at “orders of magnitude lower cost,” said Ramin Neshanti, marketing workgroup chair of the PCI SIG.

In addition, the group announced progress on its Gen 4.0 spec, expected to be the last turn of the crank for copper in pcb interconnects. It will support 16 GTransfers/second and be complete in early 2016.

The SIG also detailed a handful of enhancements to the 8GT/s Gen 3 spec and a new form factor for mobile devices called M.2 that aims to replace mini-PCIe cards.

The M-PCIe news took center stage at the event. It is expected to appear in apps processors, Wi-Fi combo devices, bridge chips and storage controllers. First SoCs using it could tape out early next year, said a Cadence product manager.

Cadence showed M-PCIe running at Gear 2 data rates up to 2.9 GHz.

M-PCIe hits 5.8 GHz

Synopsys showed M-PCIe running at Gear 3 data rates up to 5.8 GHz. A Gear 4 data rate matching the 8 GT/s of PCIe Gen 3 is in the works at MIPI.

A spec written in shorthand

The M-PCIe spec is only 60 pages long, terse by comparison to other PCI SIG standards. That’s because it largely references existing MIPI M-PHY and PCI-SIG Gen 3 protocol specs. It aims to link apps processors with basebands, W-Fi combo chips, storage and more (below).

Click on image to enlarge.

A smaller Mini Card

Click on image to enlarge.

The M.2 spec defines as many as a dozen form factors that can replace existing Mini and Half Mini PCIe cards for Wi-Fi combo chips, solid-state drives and other peripherals. The version 0.7 spec could be complete by the end of the year.

PCIe attacks Thunderbolt

Click on image to enlarge.

Oculink is a cabled PCIe Gen 3 that will deliver up to 32 Gbits/s (using a x4 configuration) over 1-3 meters of a low-cost twisted pair cable with the spec due for complete before June 2014.

Oculink will support PCIe Gen 4 and active optical cables in the future. It aims to outgun and undercut Thunderbolt, launched in early 2011 at 20 Gbits/s.

Speed doubler in the pipeline

Click on image to enlarge.

The 16 GT/s PCIe 4.0 should be complete in Q1 2015, is in a version 0.3 today and should “not require heavy equalization,” said a Neshanti. It will see use mainly in servers for 40/100 Gbit Ethernet, Infiniband and more.

Meanwhile, the PCI SIG is rolling up a number of Gen 3 enhancements into a 3.1 version. They include an L1 power state already used in Intel’s Haswell processor, better media synchronization and refinements for virtualization.

Tiny board packs punch

PLDA showed at the event its tiny Altera and Xilinx FPGA boards supporting PCI3 Gen 2.

Low cost PCIe tester

Teledyne LeCroy shows a PCIe Gen 2 protocol analyzer that sells for less than $5,000.

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